Phase lock loops (PLL) are commonly used in radio communication applications for generating stable frequencies in circuits such as RF transceivers. A PLL is a closed system which uses feedback to generate a frequency signal that is locked to a reference clock signal. FIG. 1 is a general block diagram of a well known PLL circuit.
In FIG. 1, PLL 10 will lock its internal frequency, ie. INT_CLK to a reference signal REF_CLK. PLL 10 includes a phase detector 12, a charge pump 14, a loop filter 16, a voltage controlled oscillator (VCO) 18 and a divider circuit 20. In general operation, the phase detector 12 compares the phase of the reference signal REF_CLK to the internally generated signal INT_CLK, and the charge pump 14 will generate the appropriate signals for controlling VCO 18. Eventually, convergence is reached and the INT_CLK will lock with REF_CLK. The function of the circuits of PLL 10 shown in FIG. 1 are well known in the art.
Most PLL circuits are predominantly implemented with analog circuits, and have the loop filter implemented off chip. In the PLL 10 of FIG. 1, all the components are analog with the exception of the phase detector 12 and the divider circuit 20. The loop filter 16 can be implemented digitally, thereby allowing it to be integrated on-chip with the other components. The VCO 18 preferably remains an analog circuit to provide accurate control over the output frequency signal, in response to an analog voltage signal. Therefore, the charge pump 14 should provide an analog signal for controlling the VCO 18. An example charge pump 14 is shown in FIG. 2 to illustrate how this analog signal is generated.
FIG. 2 shows the phase detector 12 coupled to the charge pump 14. Phase detector 12 compares the phase of REF_CLK to INT_CLK, and generates digital pulses UP and DOWN. The duration of the UP and DOWN pulses indicates a difference in phase between the two clock signals. The charge pump 14 has a first current source 30, switch 32, switch 34, and second current source 36, all connected in series between the high voltage supply and ground. It is assumed that the first and second current sources 30 and 36 are identical. Signal Analog_out is provided from the common terminal of switches 32 and 34, to which is connected a loop filter 38. The frequency of VCO 18 is adjusted via signal Analog_out, which itself is adjusted by the duration each switch 32 and 34 is turned on. FIG. 3a shows example signal traces for signals UP and DOWN. Signal UP rises to the high logic level at time t1 to turn on switch 32 to increase the voltage level of Analog_out via loop filter 38. At time t2, signal DOWN rises to the high logic level to turn on switch 34. Therefore, the net current being applied to loop filter 38 is zero and the adjustment to Analog_out stops. Eventually, both UP and DOWN will have substantially the same pulse duration, as shown in FIG. 3b, meaning that INT_CLK has locked to REF_CLK.
A significant disadvantage to having a PLL implemented with too many analog circuits is that the analog circuits do not scale well with each process technology generation. For example, analog circuits designed for a 90 nm fabrication process technology will not work as designed if the same circuits are fabricated in a 65 nm fabrication process technology. Digital circuits on the other hand, scale well with process technology, thereby simplifying design iteration and reducing overall cost when a circuit design is ported to the next technology.
It is, therefore, desirable to provide a PLL circuit which maximizes digital circuit content, and has a digitally implemented charge pump circuit for controlling the VCO.